Dr. Engel is collaborating with researchers in the Department of Computer Science and Engineering at Washington University in Saint Louis on the development of an improved Globally Asynchronous Locally Synchronous (GALS) design methodology for ultra large scale integrated circuits. Click on one of the links below to learn more.





*      ††††††††† Hu Wang Thesis on the design of a restartable clock for use in GALS SoCs


*      ††††††††† Powerpoint presentation given by Hu Wang at thesis defense


†††††††††††††† This work funded by NSF STTR Grant 0741055





*      ††††††††† Preliminary paper describing design of 600 MHz QVCO.


*      ††††††††† Powerpoint presentation design describing design of QVCO.


*      ††††††††† Poster describing QVCO.




*      ††††††††† Masters report describing design of earlier version of the clock generator.


*      ††††††††† Poster describing clock generator.


*      ††††††††† Picture of test chip that we fabricated and are currently testing.


*      ††††††††† Report to MOSIS on results of testing IC.





*      ††††††††† Masters report describing a dual core Fibonacci processor.


*      ††††††††† Masters report describing design of interlock.


*      ††††††††† Masterís report describing control modules used in our GALS design methodology.


*      ††††††††† Masterís report describing how to measure metastability.


*      ††††††††† Proposal to MOSIS requesting free fabrication of simple test chip.