GALS

Dr. Engel conducts research in the area of Globally Asynchronous Locally Synchronous (GALS) design methodologies for ultra large scale integrated circuits. Dr. Engel collaborates with a local company, Blendics Inc.

Click on one of the links below to learn more.

Thesis work of Sam Dunham (August 2014)

Data Synchronizer Performance in the Presence of Parameter Variability by Sam Dunham

Powerpoint presentation given by Sam Dunham at thesis defense

This work was carried out under NSF STTR Phase I I-B (Grant #0924010)

“Blended Clocked and Clockless Integrated Circuit Systems”

Hu Wang Thesis on the design of a restartable clock for use in GALS SoCs

Powerpoint presentation given by Hu Wang at thesis defense

This work funded by NSF STTR Grant #0741055

Powerpoint presentation design describing design of QVCO.

Masters report describing design of earlier version of the clock generator.

Poster describing clock generator.

Picture of test chip that we fabricated and are currently testing.

Report to MOSIS on results of testing IC.

Masters report describing design of interlock.

Master’s report describing control modules used in our GALS design methodology.

Master’s report describing how to measure metastability.