Dr. Engel is collaborating with researchers in the
Department of Computer Science and Engineering at
††††††††† Preliminary paper describing design of 600 MHz QVCO.
††††††††† Powerpoint presentation design describing design of QVCO.
††††††††† Masters report describing design of earlier version of the clock generator.
††††††††† Poster describing clock generator.
††††††††† Picture of test chip that we fabricated and are currently testing.
††††††††† Report to MOSIS on results of testing IC.
††††††††† Masters report describing a dual core Fibonacci processor.
††††††††† Masterís report describing control modules used in our GALS design methodology.
††††††††† Proposal to MOSIS requesting free fabrication of simple test chip.